ics960002 0677d?10/10/02 integrated circuit systems, inc. block diagram power pc based lbp pentium is a trademark of intel corporation. xta l osc pll1 spread spectrum pll2 control logic configuration resistor usb div 2 ssc [1:0] usb_en clk_sel [1:0] pci_en asic2_en asic_sel xin xo u t cpu asic1 asic2 (a, b) pci (1:0) stop pci divider cpu divider vddcor, dig, usb=3.3v vddcpu, asic1, asic2, pci = 2.5v or3.3v 4 2 3 3 4 gndcpu, asic1, asic2, pci = 0v gndcor, dig, usb=0v 2 features - cpu, asic, and pci can run at 2.5v or 3.3v selectable. - generates the following system clocks: 1-cpu (2.5v/3.3v) (66.66mhz to 100.00mhz) 2-pci (2.5v/3.3v) (33.33mhz) 2-asic (2.5v/3.3v) (66.66mhz to 100.00mhz) 1-asic (2.5v/3.3v) (33.33mhz to 100.00mhz) 1-usb (3.3v) (48mhz) - skew characteristics: cpu to asic < 250ps - jitter characteristics cpu/asic <150ps (cycle to cycle) -spread spectrum features off -0.5%, 1.0%, and 1.25% downspread - power management enable/disable pci, asic2, and/or usb independently - uses external 14.318mhz crystal or reference clock vdd gnd 6, 7 1, 18 3.3v internal logic and core powe r 8 11 pci outputs 14 12 usb outputs 19 21 asic1 outputs 25 22 asic2 outputs 26 28 cpu ouputs pin number description power groups gndcor 1 28 gnd ssc1/asic_3.3v_2.5# 2 27 cpuclk0 ssc0/cpu_3.3v_2.5# 3 26 vddcpu x1 4 25 vddasic2 x2 5 24 asic2a/asic2a_en * vddcor 6 23 asic2b vdddig 7 22 gnd vddpci 8 21 gnd pciclk0/pci_3.3v_2.5# 9 20 asic1 pciclk1/pci_en* 10 19 vddasic1 gnd 11 18 gnd gnd 12 17 asic1_sel* usb0/usb_en* 13 16 clk_sel1 vddusb 14 15 clk_sel0 ics60002 pin configuration note: * 60kohm to 120kohm internal pullup resistor 209mil ssop
2 ics960002 0677d?10/10/02 pin descriptions pin # pin name pin type description 1 gndcor pwr ground pin for the pll core. 2 ssc1/asic_3.3v_2.5# in spread spectrum amplitude control with latched vddasic 3.3v/2.5v# select. 3 ssc0/cpu_3.3v_2.5# in spread spectrum amplitude control with latched vddcpu 3.3v/2.5v# select. 4 x1 in crystal input,nominally 14.318mhz. 5 x2 out crystal output, nominally 14.318mhz 6 vddcor pwr 3.3v power for the pll core. 7 vdddig pwr 3.3v internal digital power. 8 vddpci pwr power supply for pci clocks, nominal 3.3v 9 pciclk0/pci_3.3v_2.5# i/o pci clock output with latched vddcpu 3.3v/2.5v# select. 10 pciclk1/pci_en* i/o pci clock output with latched pci enable function at startup. 11 gnd pwr ground pin. 12 gnd pwr ground pin. 13 usb0/usb_en* i/o usb clock output with latched usb enable function at startup. 14 vddusb pwr supply for usb clocks,3.3v nominal 15 clk_sel0 in function select pin. see table for details. 16 clk_sel1 in function select pin. see table for details. 17 asic1_sel* in function select pin. see table for details. 18 gnd pwr ground pin. 19 vddasic1 pwr supply for asic1clocks,3.3v nominal 20 asic1 out asic1 clock output. 21 gnd pwr ground pin. 22 gnd pwr ground pin. 23 asic2b out asic2b clock output. 24 asic2a/asic2a_en* i/o asic2a clock output with latched pci enable function at startup . 25 vddasic2 pwr supply for asic2 clocks,3.3v nominal 26 vddcpu pwr supply for cpu clocks, 3.3v nominal 27 cpuclk0 out cpu clock outputs. 3.3v 28 gnd pwr ground pin. pin 2, 3 and 9 functionality: when the device powers-up, the pin work as latch pin to decide supply voltage on vddxxx, and then will work as select pin of ss(or output pin). when high(vdd=3.3v) is latched, the output buffer of xxx will be optimized at vddxxx=3.3v, when low(gnd) is latched, the output buffer of xxx will be optimized at vddxxx=2.5v. the voltage of the latch point is approximate vddcore/dig=1.8v. and it will take effect within the time of clock stabilization. note: internal pull-up resitors on pin 10, 13, 17, and 24. no internal resistor for pin 2, 3, 9, 15 or 16.
3 ics960002 0677d?10/10/02 frequency tables asic1_sel=1 asic1_sel=0 0 0 66.66 66.66 33.33 66.66 0 1 100.00 100.00 50.00 100.00 1 0 83.33 83.33 41.67 83.33 1 1 88.88 88.88 44.44 88.88 clk_sel1 clk_sel0 asic1 (mhz) cpu (mhz) asic2 [a, b ] (mhz) spread spectrum selection table ssc1 ssc0 00 01 10 11 -0.50% down spread -1.00% down spread -1.25% down spread spread spectrum modulation [mhz] off power management table usb_en pci_en asic2_en usb pciclk(1,0) asic2 0 xx tri-state x x 1 xx 48mhz x x x 0 x x tri-state x x 1 x x 33.3mhz x xx0 x x tri-state xx1 x x selected
4 ics960002 0677d?10/10/02 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 5.5v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - ac specification t a = 0 - 70c; v dd = 3.3 v or 2.5v +/-5%; c l =20pf(unless otherwise stated) parameters symbol conditions min. typ. max. units input frequency z o 12 14.31818 16 mhz sst modulation sweep rate fmod - 32.2 - khz transition time t trans to 1st crossing of target freq. 1.1 3 ms settling time t s from 1st crossing to 1% target freq. 1.5 3 ms c in logic inputs <2 5 pf c out output pin capacitance <2 6 pf c inx x1 & x2 pins 27 30 45 pf output rise time t r2b 0.8v to 2.0v with no load 0.5 1.5 ns output fall time tf 2b 2.0v to 0.8v with no load 0.5 1.5 ns duty cycle d t2b at vdd/2 45 50 55 % cpu and asic skew t sk2b equal power supply for both asicandcpuatsame frequency; cl =20 pf 200 250 ps t jitabs2b cpu and asic only. -150 - 150 ps t jitabs2b pci -175 -175 t jitabs2b usb -150 -150 t jcyc-cyc2b cpu and asic only. 90 120 ps t jcyc-cyc2b pci 110 200 ps t jcyc-cyc2b usb 95 150 ps max. absolute period jitter max. jitter, cycle to cycle input capacitance
5 ics960002 0677d?10/10/02 electrical characteristics - dc specification t a = 0 - 70c; v dd =see table below; c l = 20 pf (unless otherwise stated) parameters symbol conditions min. typ. max. units vddcor vdddig vddusb vddpci vddasic1 vddasic2 vddcpu input high voltage v ih for all normal input 2 v dd + 0.3 v input low voltage v il for all normal input v ss - 0.3 0.8 v output high voltage v oh3.3 i oh = -25ma 2.4 v output low voltage v ol3.3 i ol = 25ma 0.4 v output high voltage v oh2.5 i oh = -25ma 2 v output low voltage v ol2.5 i ol = 25ma 0.4 v operating supply current i dd no load 35 50 ma operating voltage nominal voltage is 3.3v 2.97 3.3v nominal voltage is 3.3v or 2.5v 2.25 2.5v 2.97 3.3v 3.63 v v v 2.75 3.63
6 ics960002 0677d?10/10/02 fig. 1 via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used both to provide the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. when no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, then only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
7 ics960002 0677d?10/10/02 ordering information ics960002 yf-t seating plane seating plane a1 a a2 e -c- - c - b .10 (.004) c .10 (.004) c c l index area index area 12 1 2 n d e1 e 209 mil ssop min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference do c.: jedec p ublicatio n 95, m o-150 see variations see variations n d mm. d (inch) see variations see variations 0.65 basic 0.0256 basic 209 mil ssop symbol in millimeters in inches common dimensions common dimensions designation for tape and reel packaging package type f=ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y f - t
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